The teaching is a combination of class teaching and exercises.
The teaching is based on a course project, which is done in
groups.
Kursets varighed:
[Kurset følger ikke DTUs normale
skemastruktur]
Evalueringsform:
Bedømmelsesform:
Tidligere kursus:
EVHDLE-U01
Obligatoriske forudsætninger:
Anbefalede forudsætninger:
Overordnede kursusmål:
To enable the student to develop VHDL-models for simulations,
synthesis and implementation. The main project is to implement a
model first as a behavioural model and later refine this model to a
RTL structural model which can be synthesised. The design is then
tested in a Xilinx FPGA.
Læringsmål:
En studerende, der fuldt ud har opfyldt kursets mål, vil kunne:
To learn the student to create a well structured
VHDL-program
To learn the student the connection between hardware and
software
To learn the student to create programs in flat as well as
structured design.
To learn the student to write reuseable programs
To learn the student about FPGA's
To learn the student about error-handling technikes in
FPGA's
.
.
Kursusindhold:
The structure of VHDL:
- lexical description and syntax.
- design units, control structures, data objects and instructions.
- subprograms
Model description:
- behavioral og structural domain models.
- abstraction hierarchy and data transfer.
Simulating
- script
- testbench
Design, simulations and implementation of a basic model
The course is based on WebPack version 12 or later design
tools
Litteraturhenvisninger:
Notes.
Supplement:
The Designers Guide to VHDL 2nd edition. Peter J. Ashenden. ISBN
1-55860-674-2. Morgan Kaufmann Publishers
Bemærkninger:
In the beginning of the semester the students form their own
project groups. The group size should be 3-5 students. Each group
pick up a test-board in the workshop
The exam:
Group presentation of the project. Each student will give a 5
minutes presentation of a part of the project. These presentations
must be different and together they must cover important topics of
the project.
