2010/2011

02211 Advanced computer architecture

Engelsk titel: 


Advanced computer architecture

Sprog:


Point (ECTS )


5

Kursustype:   

Civil- Videregående Kursus
Kurset udbydes under åben uddannelse


Skemaplacering:

F4A

 

Undervisningsform:

Lectures and project

Kursets varighed:

13-uger

Eksamensplacering:

F4A 

Evalueringsform:

Hjælpemidler:

Bedømmelsesform:

Obligatoriske forudsætninger:

Ønskelige forudsætninger:


Deltagerbegrænsning:

Minimum  5, Maksimum:  25
 

Overordnede kursusmål:

Computer architecture, the art and science of designing hardware, is an exciting and fast changing research and development field. In this course we intend to transfer this excitement to the students.

Students will learn the organization and design of contemporary processor architectures. The foundations such as instruction set, pipelining, and memory hierarchies are reviewed. We will cover advanced concepts such as instruction-level parallelism, out-of-order execution, and chip-multiprocessing. As the current trend in computer architecture is towards chip-multiprocessing, the architecture of shared memory multiprocessors and chip level interconnect (network-on-chip) will be a central focus of the course.

Most processors (99+%) are used in embedded systems, and many of those embedded systems are real-time systems. Therefore, processors need to be designed in a way that worst-case execution time analysis is feasible. We will cover current research in the field of time-predictable architectures.


Læringsmål:

En studerende, der fuldt ud har opfyldt kursets mål, vil kunne:
  • Understand advanced computer architecture aspects
  • Design pipelined processors
  • Describe and explain instruction level parallelism with static scheduling and out-of-order execution
  • Understand the architecture and limitations of chip-multiprocessing
  • Describe and explain network-on-chip architectures
  • Explain time-predictable computer architcture
  • Evaluate a scientific paper (from conference or journal)
  • Prepare a conference-style paper

Kursusindhold:

Review of pipelining and caches; instruction-level parallelism; chip-multiprocessing; network-on-chip; time-predictable computer architecture


Litteratur:

J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 4th Edition, Morgan Kaufmann Publishing Co., Menlo Park, CA. 2006.

In addition to the textbook, this course includes a number of readings from research papers.


Bemærkninger:

Students will work in groups of two or three on a hardware or software lab project. A hardware project can be building a pipelined design in an FPGA. Software projects will explore embedded chip-multiprocessor programming and programming models. Besides a working solution, students will prepare a conference-style paper on their project. The project and paper will be presented in class. Exceptional projects shall lead to publications in computer architecture conferences.


Kursusansvarlig:

Martin Schoeberl, 322, 232, (+45) 4525 3743, masca@imm.dtu.dk  
Jens Sparsø, 322, 215, (+45) 4525 3747, jsp@imm.dtu.dk  

Institut:

02 Institut for Informatik og Matematisk Modellering

Tilmelding:

I CampusNet
Sidst opdateret: 20. december, 2010